1. Field of the Invention
The present invention generally relates to radio frequency communication receivers, systems, and methods employing ultra-wide bandwidth (UWB) signaling techniques. More particularly, the present invention relates to a method, system and computer program product for ultra wide bandwidth communications using a low power, high-resolution, timing generator.
2. Discussion of the Background
In UWB communication systems, a UWB transceiver sends data to and receives data from a remote UWB transceiver. The UWB transceivers receive incoming signals and proceed to extract information therefrom. The clocks of the different UWB transceivers are usually not initially synchronized. Accordingly, in order to acquire accurately incoming signals, the timing of the UWB transceivers must be precisely synchronized (e.g., on the order of picoseconds). This function typically requires use of what is know as a “adjustable time delay generator” to provide highly accurate control for effectuating synchronized communications between UWB transceivers.
However, as presently recognized most UWB transceivers use high-speed time delay generator circuits implemented using high-speed, high-power and high-cost analog and digital devices using time domain techniques. These devices take an input trigger signal and generate an output trigger signal that is delayed by a programmable time relative to the input trigger signal. This is done, because most UWB transceivers are directed to pulse position modulation systems, leading most inventors to think only in terms of adjusting the time-position of a pulse by using time domain devices and techniques. Therefore, such circuits are built the way inventors typically think—pulse position equals time domain.
For example, Fullerton et al (U.S. Pat. No. 5,677,927 issued Oct. 14, 1997) disclose a timing generator based on variable delays and pulse positioning in the time domain. In this respect, background art FIGS. 19-21 correspond to respective FIGS. 23, 24 and 20 of Fullerton et al. As shown in FIG. 19, for example, a code time modulator element 1008 and sub-carrier time modulator 1016 are used. Similarly, in FIG. 20, for example, a binary-to-time-delay generator 2424 is used.
Accordingly, such exemplary inventions are working in the time domain, for example, throwing a switch to charge a capacitor to some threshold to toggle a gate (e.g., a 555 timer) and may include a digital-to-analog converter (DAC) to drive a comparator voltage (e.g., an Analog Devices AD9500). Thus, such time delay generators are built to program in a binary value and when hit with a trigger pulse the device waits a predetermined time before an output switch toggles in response thereto.
FIG. 21 shows a plot that illustrates problems associated with such time domain implementations. From FIG. 21, it is seen that such devices without error correction will delay across a range of about 300 picoseconds with errors on the order of 50 picoseconds. However, such devices must be programmable and repeatable to a few picoseconds. To correct for such errors, for example, in the circuit of FIG. 20 there is included a linearization ROM 2426. This ROM typically is custom programmed for each build to compensate for the non-repeatability of the analog circuits used in such time domain implementations. Cancellation of such errors over temperature is even more complicated, since drift must be cancelled as well.
To further complicate matters, a string of time delay devices, coarse to fine, is often used in order to cover an operational range of t1 to t2, where t2−t1 may be as long as hundreds of microseconds. In such a circuit, one device in the string provides the coarsest adjustment, and another device in the string provides the finest adjustment. However, such a string of devices must be monotonic and repeatable to a few picoseconds, which is difficult to achieve with such an implementation. Further, linearization of such a circuit over temperature and over a dynamic range of 105 is time consuming and costly.
A further problem with the above-noted implementations, such as the invention of Fullerton et al, is that such systems suffer from jitter in the delay time. Each programmable delay circuit must use very high-speed transistors that exhibit very low noise in order for the output signal to trigger precisely at the threshold voltage or current. The problem, however, is that the threshold voltage and threshold-comparator circuits are noisy, and this noise causes the time delay to be inconsistent or, in other words, jitter. This jitter is especially difficult to control on the coarse control devices, because the delay changes by the largest amount proportional to the control signal. As a result, higher currents and expensive devices must be used. Therefore, to summarize, such systems typically require high power, are noisy, have linearity problems, and require custom manufacturing and tuning.
Accordingly, such conventional timing generator implementations typically are not well suited for many battery-operated, portable and hand held device applications, such as personal digital assistants (PDAs), cellular phones, lap top computers, etc. This is because such devices typically have fixed device circuitry, limited power supplies, limited circuit real estate and therefore must be implemented using low-power, low-cost devices.
Another problem with the above-noted implementations, such as the invention of Fullerton et al, is that such systems suffer from non-scalability. A scaled system allows for receiving signals at several different delay-times simultaneously, such as a rake processor receiver, wherein the receiver includes multiple arms to track signals coming from different multi-path locations. In FIG. 20, however, the system shown includes a binary-to-time delay generator 2424, linearization ROM 2426, programmable divider 2438 and voltage-controlled oscillator (VCO) 2440.
Accordingly, to implement a scaled system, using the time delay generator approach shown in FIG. 20, the entire set of devices typically must be duplicated. Therefore, the triggered waveform generator 2412, the binary-to-time delay generator 2424, the linearization ROM 2426, the programmable divider 2438, the VCO 2440, etc., typically have to be duplicated for every arm of the rake processor receiver. Accordingly, such implementations lead to complex, high power, high cost, devices not well suited for applications, such as personal digital assistants (PDAs), cellular phones, lap top computers, etc., that have fixed device circuitry, limited power supplies, and limited circuit real estate.